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CMOS compatible ZrN metallization
CMOS compatible ZrN metallization
Single layer metal patterning for BEOL
Fraunhofer Institute for Photonic Microsystems IPMS
Qu-Pilot
The service is dedicated to serve as a flexible CMOS compatible platform for design, process, material and consumable evaluation on scaled superconducting metallization module. IPMS has established a reliable processing sequence on 300mm industry standard equipment to produce high quality devices with high yield which can serve as a testbed or as prototype vehicle. Basic spezifications: Wafer size: 200mm, 300mm, Metallization line width: ≥ 50nm, LER at min CD: 3nm, SC thickness range:
Tc comparison of scaled ZrN lines
Tc comparison of scaled ZrN lines
Typical SC testchip fabricated by eBeam lithography (left), universal contacting scheme allowing flexible usage of different cryo setups
Typical SC testchip fabricated by eBeam lithography (left), universal contacting scheme allowing flexible usage of different cryo setups
Computing
4
Semiconducting  Superconducting 
Prototyping  Fabrication
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