CMOS compatible In bumps for chip bonding
CMOS compatible In bumps for chip bonding
CMOS-compatible electroplated In bumps
Fraunhofer Institute for Photonic Microsystems IPMS
Qu-Pilot
The processing flow is dedicated for the fabrication of superconducting chip-to-wafer or chip-to-chip connections via In bump technology with Tc of 2.6K. IPMS has qualified a process module with high bump yield for sizes down to 10µm consistently reaching high uniformity even at low structure open area. The established processing sequence is based on 300mm industry standard toolset and can serve as a testbed or as prototype vehicle. Standard Cu based UBM layers or superconducting UBM are available on request.
Top down image of 30µm sized In bumps
Top down image of 30µm sized In bumps
Sideview of 30µm sized In bumps
Sideview of 30µm sized In bumps
Computing
6
Semiconducting  Superconducting 
Prototyping  Fabrication